The manufacture of integrated circuits on semiconductor wafers has continued to allow electrical devices to become more compact, yet with improved performance and greater capabilities. As a result, manufacturers are constantly improving on the manufacturing techniques and processes for the semiconductor devices forming these integrated circuits. In addition, as manufacturing processes for semiconductor devices and interconnects become more complex, techniques for testing the results of such processes become more important. Specifically, modem processes typically include the manufacture of test wafers, built having multiple test structures that allow manufacturers to perform a variety of tests in order to evaluate the potential performance of finished wafers manufactured with the same processes. Although test wafers permit such testing, current manufacturing techniques often include producing test structures within production wafers, allowing manufacturers to perform performance testing within actual wafers to be sold to customers. With this approach, manufacturers may obtain more accurate performance evaluations by testing structures within the actual wafers produced for customers.
One particular test structure commonly employed by today's manufacturers is the evaluation of stress-induced voiding among the interconnections between vias and interlevel metal conductors in the various levels of semiconductor wafers. Stress-induced voiding typically refers to the development of defects at these interconnection points to the degree of causing voids, e.g., open circuits. Such stress-induced voiding may manifest itself in several ways.
Referring initially to FIG. 1, illustrated is an interlevel interconnection 100 suffering failure from one type of stress-induced voiding that may occur during the manufacture of semiconductor wafers. The interconnection 100 includes a thin conductor 2 coupled to a bulk metal layer 4 with an interconnecting via 6. As illustrated, the thin conductor 2 is formed on a higher level than the bulk metal layer 4. As the interconnection 100 undergoes stress during operation, for example, thermal stress, a failure area 8 develops as a result of stress-induced voiding. More specifically, with the thin conductor 2 on a higher level than the bulk metal 4, vacancies 10 around the connection point between the via 6 and the bulk metal 4 migrate towards the connection point forming microvoids. As the voids increase, the failure area 8 eventually develops resulting in increased resistance and in some cases an open circuit between the thin conductor 2 and the bulk metal 4.
Looking now at FIG. 2, illustrated is another interlevel interconnection 200 suffering failure from another type of stress-induced voiding. The interconnection 200 also includes a thin conductor 12 coupled to a bulk metal layer 14 with an interconnecting via 16. However, unlike the interconnection 100 in FIG. 1, the interconnection 200 in FIG. 2 has the thin conductor 12 formed on a lower level than the bulk metal layer 14. With this formation, as the interconnection 200 undergoes stress during operation, the tensile stress in the bulk metal 14 increases causing the bulk metal 14 to move in the directions indicated by arrows A1 and A2. As the tensile stress in the bulk metal 14 increases, and the bulk metal 14 moves further in the directions denoted by arrows A1 and A2, the stress translates to the via 16, pulling it upwards, as denoted by arrow A3. As the via 16 is forced upwards by the tensile stress, the via 16 eventually pulls away from the thin conductor 12 causing an open circuit failure 18 between the thin conductor 12 and bulk metal 14.
In addition to the various types of failures caused by stress-induced voiding, the larger the metal layers involved, the more severe the migration of microvoids, in the case of a thin conductor over a bulk metal layer, and the more severe the tensile stress, in the case of the bulk metal over the thin conductor. As a result, the larger the metals (e.g., length and width) employed to form the interconnections, the higher the probability for failure from stress-induced voiding. As mentioned above, to evaluate the performance of the selected sizes, manufacturers employ test structures in production wafers.
FIG. 3 illustrates a conventional test structure 300 for evaluating stress-induced voiding among semiconductor wafer interconnections. As may be seen, two contact pads 20 are positioned on the same level, and located over a bulk metal 22. The bulk metal 22 is coupled to the contact pads 20 using vias 24. Although in the illustrated test structure 300, the bulk metal 22 is located below the contact pads 20, other conventional test structures are also in use having the bulk metal 22 positioned over the contact pads 20.
Unfortunately, regardless of which conventional test structure is employed, both suffer from similar deficiencies. More specifically, in order to evaluate the effects of stress-induced voiding on the multitude of metal structure sizes, each structure 300 includes bulk metal 22 having a selected length and width. The structure 300 may then be used to evaluate stress-induced voiding on that particular size of bulk metal 22. However, to evaluate stress-induced voiding on any other size, a separate test structure is formed, having bulk metal with a length and/or width different than bulk metal in the first structure.
As mentioned above, since the probability of failure due to stress-induced voiding constantly varies in proportion to the size of the interconnected metal layers, a great number of test structures, typically over 100, must be constructed in the production wafer to provide a complete spectrum of failure evaluation. As may be expected, such a large number of test structures occupies a tremendous amount of wafer real estate, reducing overall wafer yield and consequently increasing the overall cost of semiconductor device manufacture. Of course, less test structures may be formed on production wafers, but then the accuracy of evaluating stress-induced voiding failure probability is substantially decreased. Accordingly, what is needed in the art is a test structure, and related methods, for evaluating the probability of stress-induced voiding failures in semiconductor wafer interconnections that do not suffer from the deficiencies associated with conventional techniques.